1. Field of the Invention
This invention relates to forming a FET (Field Effect Transistor), and more particularly to a method of protecting the gate electrode of the FET from implants of unwanted impurities during implantation of regions of the FET. The FET is a Metal Insulator Semiconductor FET (MISFET) such as a Metal Oxide Semiconductor FET (MOSFET) where the insulator is an oxide and the xe2x80x9cMetalxe2x80x9d is a conductor such as doped polysilicon or a metal conductor.
2. Description of Related Art
U.S. Pat. No. 5,891,784 of Cheung et al. for xe2x80x9cTransistor Fabrication Methodxe2x80x9d describes forming an anti-channeling hard mask in the form of an anti-channeling monolayer or a bilayer of doped silicon dioxide (BPSG or PSG), silicon nitride or silicon oxynitride between 100 xc3x85 and 4000 xc3x85 above a gate electrode stack, with no sidewall spacers having been formed when shallow junctions are being formed in the substrate. The anti-channeling hard mask can comprise a bilayer of undoped silicon oxide covered with doped silicon oxide or covered with silicon nitride. Alternatively an anti-channeling hard mask layer of doped silicon oxide may be progressively doped more heavily from bottom to top. The purpose is to prevent penetration of dopants through the gate electrode into the channel without protecting the gate electrode from the implanted dopant.
European patent application No. EP 0 771 021 of Chittipeddi et al. for xe2x80x9cTransistor Fabrication Methodxe2x80x9d describes covering the gate electrode with a protective layer before ion implantation to prevent channeling. A protective oxide layer is formed on both the gate electrode stack and the substrate, but it is thicker on the gate electrode stack than on the substrate. The process uses differential oxidation to create a thicker silicon oxide layer on top of the polysilicon than on the underlying silicon to block implants from reaching the gate electrode, but will block them from reaching the extension also.
JP8097421A of Hiroshi et al for xe2x80x9cManufacture of Semiconductor Devicexe2x80x9d is directed to preventing the substrate of a device from being damaged during RIE, by performing a partial RIE after deposition of a silicon oxide spacer, implanting S/D and etching the rest of the silicon oxide. That process will not block the S/D implants from reaching the gate electrode.
U.S. patent application publication No. 2001/0011756 A1 of Yu for xe2x80x9cMethod for Forming Shallow Source/Drain Extension for MOS Transistorxe2x80x9d performs implantation of an amorphization substance such as silicon or germanium into the substrate to form source and drain extensions under the gate in a process using a silicon oxynitride (SiOxNy) hard mask to prevent implantation of the gate. Then after the amorphization step, sidewall spacers are formed alongside the gate electrode. Next, dopant is implanted into the substrate to form S/D with the hard mask protecting the gate electrode using the silicon oxynitride (SiOxNy) hard mask again, to prevent implantation of the gate.
JP10-189959A of Horiuchi Katsutada for xe2x80x9cSemiconductor Devicexe2x80x9d describes use of a hard mask and the gate electrode itself to block Arsenic (As) from reaching the substrate to prevent the substrate floating effect. Subsequently, there is a step of vertical ion implantation of Argon (Ar) followed by heat treatment to create a crystal defect region of polycrystals at the interface with an insulating film. The substrate floating effect can exist in an SOI-MOS structure in which a MOS transistor is formed on an insulating substrate or film in which the substrate region of the MOS transistor is floated. As the drain voltage rises, holes among pairs of electrons and holes generated by the impact ionization of channel carriers stay in the substrate region and bias the substrate region positive which causes the threshold voltage to drop, so the drain currents increase suddenly, rendering the potential of the substrate region of the SOI-MOS transistor unstable. This instability is referred to as the xe2x80x9csubstrate floating effectxe2x80x9d. In addition, ionization is generated near the end portion of the drain region due to a small amount of the leakage current between the and drain.
U.S. Pat. No. 6,232,188 of Murtaza et al for xe2x80x9cCMP-Free Disposable Gate Processxe2x80x9d describes a disposable gate process which avoid use of Chemical Mechanical Polishing (CMP). A High Density Plasma Chemical Vapor Deposition (HDP-CVD) field dielectric composed of silicon oxide blocks implants from reaching S/D while leaving portions of the disposable gate exposed. The disposable gate is removed and then the gate electrode is deposited subsequently.
U.S. Pat. No. 6,118,161 of Chapman et al. for xe2x80x9cSelf-Aligned Trenched-Channel Lateral-Current-Flow Transistorxe2x80x9d describes a disposable gate process in which source/drain (S/D) regions xe2x80x9cmay be implanted using the disposable gate as an implant block . . . xe2x80x9d Later the disposable gate is completely removed.
R. B. Fair, xe2x80x9cModeling Boron Diffusion in Ultrathin Nitrided Oxide p+Si Gate Technologyxe2x80x9d, IEEE Electron Device Lett., 18, 244 (1997) discusses thin gate dielectric materials, i.e. nitrided oxide films and the effects of fluorine and boron thereon.
M. Navi, and S. T. Dunham, Investigation of Boron Penetration Through Thin Gate Dielectrics Including Role of Nitrogen and Fluorinexe2x80x9d J. Electrochem. Soc., 145, 2545 (1998).
The extension and source drain implants which also get implanted into the gate can cause problems for MIS/MOS devices. Thus, it is desirable to completely uncouple the gate implants from the extension and source drain implants of an FET device. For example, for a PFET, the extension implant regions and the source/drain implant regions can contain boron difluoride (BF2.) Boron difluoride (BF2) is amorphizing at the doses used in extension or S/D formation. Therefore the channeling of boron is reduced during a BF2 implant. Boron diffusion is also suppressed during subsequent anneals because of the presence of fluorine in the extension implant regions and the source/drain implant regions. Therefore, it is easier to get ultra-shallow junctions with BF2 than with boron alone. However, as the unwanted presence of fluorine in the gate electrode increases, there is an increasing problem of diffusion of extra fluorine from the BF2 implant passing from the gate electrode through the gate dielectric into the underlying channel region. The extra fluorine from the BF2 implant in the channel region is detrimental to MIS/MOS devices. It is well known that incorporation of fluorine into gate dielectric layers enhances boron diffusion in a process referred to as xe2x80x9cboron penetrationxe2x80x9d. Boron penetration compromises the characteristics of gate dielectric layers and adversely affects the characteristics of the devices in which the condition of boron penetration exists. This is especially a big problem with ultra-thin silicon oxides (15 xc3x85) and high-k_dielectrics that are currently being developed in the semiconductor industry. Accordingly, there is a need to protect the gate electrode from fluorine containing implants to prevent penetration thereof through the gate dielectric reaching the channel region (therebelow) in the substrate of the FET device.
Sometimes it is desirable to implant the S/D and/or extension region with a diffusion retarding species/element such as carbon in order to obtain ultra-shallow junctions. However, if carbon is introduced into a polysilicon gate electrode, dopant diffusion in the gate electrode can be suppressed. If the dopant does not diffuse to the bottom of the gate electrode, the resulting polysilicon depletion will be detrimental to the performance of the MOS device. For optimal device design, a polysilicon gate electrode must be protected from diffusion retarding species.
A polysilicon gate electrode is usually doped heavily to increase the polysilicon activation and minimize polysilicon depletion effects. If the S/D implant is also implanted into a polysilicon gate electrode, the dopant concentration reach a high enough concentration to affect silicidation on the gate electrode adversely. Proper silicide formation is extremely important in obtaining low resistance polycide gate electrodes and reducing the problem of propagation delay. Thus, it is desirable to protect a polysilicon gate electrode from the S/D implant to get good silicide formation.
Integrating metal gates into a CMOS process has gained much interest lately because of the complete elimination of the polysilicon depletion effects and therefore decreasing the electrical thickness of the gate dielectric inversion layer thickness (tinv) Wolf xe2x80x9cSilicon Processing for the VLSI Era, Vol. 3, pp. 150-151 Lattice Press (1995). If a metal gate is formed before S/D or extension implants, it will be necessary to protect the metal from implants so that the structural integrity and the electrical properties of the metal will not be affected adversely.
The present invention solves the problem of protecting the gate from harmful extension and S/D implants. This is extremely important for advanced logic technologies. In order to obtain ultra-shallow junctions and ultra-sharp halos, these technologies require implants that contain carbon and fluorine. To solve the problem of preventing species such as carbon and fluorine (which comprise unwanted impurities in the gate electrode) from being introduced into the gate electrode, the present invention provides a way to block implants of carbon and fluorine into the gate electrode, whether it is formed of either doped polysilicon or metal.
In the prior art, as can be seen from the above description of the art, use of a hard mask to create a implant block layer is a very well known technique. The process of the present invention is different from the hard mask process.
The process of the present invention has four major advantages:
1) The process of the present invention can be performed at any point during the CMOS process flow. The hard mask process can be performed only during gate electrode patterning. Therefore the hard mask film is subject to other processes that can harm the hard mask before it can be employed as an implant block layer.
2) The process of the present invention can be repeated many times during the CMOS process flow whereas the hard mask process can be performed only once.
3) The process of the present invention is performed after the gate electrode patterning. The hard mask process is performed during gate electrode patterning. The hard mask film is usually chosen to minimize the Critical Dimension (CD) of lithography and to minimize the CD variation across the wafer. That restricts the type of film that can be used as a hard mask or as a implant block layer (usually just oxide). In the process of the present invention, any planar film can be used, e.g. ARC, a spin-on dielectric polymer (e.g SiLK semiconductor dielectric, the Dow Chemical Co. which is an aromatic hydrocarbon thermosetting polymer), silicon oxide, etc.
4) The process of the present invention can use organic films as an implant block layer, which can be very selectively removed with respect to silicon oxide, silicon nitride, and silicon. On the other hand, a hard mask process cannot use organic films as an implant block layer since these films are thermally unstable.
In accordance with this invention, a method is provided for the manufacture of a Metal Insulator Field Effect Transistor (MISFET) or a Metal Oxide Field Effect Transistor (MOSFET) by blocking implants from the gate electrode stack of a gate dielectric and a gate electrode of an FET device by the following steps. Form a first planarizing film covers the substrate and the gate electrode stack. Planarize the first planarizing layer by polishing until the upper surface of the gate electrode is exposed. Etch back the gate electrode below the level of the upper surface of the first planarizing film. Deposit a second planarizing film on top of the gate electrode and the first planarizing film. Polish the second planarizing film down to a level which exposes the first planarizing film while leaving a substantial thickness of the second planarizing film to form a cap comprising an implantation block covering the top surface of the gate electrode. Selectively remove the first planarizing film to open access for implantation into lateral regions in the surface of the substrate aside from the gate electrode stack whereby the counterdoped regions can be formed. Form the counterdoped regions by implanting dopant into the substrate using the implantation block to block implantation of the dopant into the gate electrode. The implantation block formed from the second planarizing film protects the gate electrode of the FET device from unwanted implanted impurities during implanting of the counterdoped regions. The first planarizing film is composed of a material selected from the group consisting of HDP (high density plasma) silicon oxide and HDP silicon nitride, an interlevel-dielectric layer material including ONO (silicon Oxide/silicon Nitride/silicon Oxide), and photoresist. The gate electrode is composed of a material selected from the group consisting of polysilicon and metal. The second planarizing film is composed of a material selected from the group consisting of HDP silicon oxide, HDP silicon nitride, and an organic layer including ARCs (Anti-Reflective Coatings). The second planarizing film is composed of a material different from the first planarizing film.